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CXD2412AQ
Timing Generator for LCD Panels
Description The CXD2412AQ is a timing signal generator for LCD panel drivers. Features * Generates the LCX007 drive pulse. * Supports NTSC/PAL. (With PAL, a video signal on which scanning line conversion has been performed is used.) * Supports WIDE. * Supports HD (20 MHz band). * Supports Muse-NTSC conversion signal (MNDC). * Supports up/down and/or right/left inversion. * Supports three-panel projector. * Generates timing signal of external sample-andhold circuit. * Generates line inversion and field inversion signals. * AC drive for LCD panel during no signal. * AFC circuit supporting static and dynamic fluctuations. Applications LCD projectors Structure Silicon gate CMOS IC Absolute Maximum Ratings (Ta = 25 C) * * * * * Supply voltage Input voltage Output voltage Operating temperature Storage temperature VDD VSS-0.5 to +7.0 V VI VSS - 0.5 to VDD + 0.5 V VO VSS - 0.5 to VDD + 0.5 V Topr -20 to +75 C Tstg -55 to +150 C 100 pin QFP (Plastic)
Recommended Operating Conditions * Supply voltage VDD 5.0 0.5 * Operating temperature Topr -20 to +75
V C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E94Y04-ST
CXD2412AQ
Block Diagram
RPD1 9 7 PEO1
RPD2 86 RPD3 94 FPD1 6 PHASE COMPARATOR LOOP FILTER
84 PEO2 95 PEO3 8 PWM1
FPD2 83 FPD3 97 TC1 5
85 PWM2 96 PWM3 48 N.C. 51 N.C. 52 N.C. PLL-COUNTER 55 N.C. 56 N.C. 57 N.C. 58 N.C. 59 N.C. 60 N.C. 75 SLFR FIELD & LINE CONTROLLER 32 RGT 47 DWN 33 XRGT
TC2 82 TC3 98 HSYNC 16 N.C. N.C. 2 1 H-SYNC DETECTOR H-SKEW DETECTOR HALF-H KILLER
CKI1 12 CKI2 89 CKI3 92 CKO1 11 CKO2 88 CKO3 91 VSYNC 17 TST6 14 TST1 24 TST2 25 TST3 26 TST4 27 TST5 30 XCLR 31 VP1 49 VP2 50 VST 46 SLAUX 73 VSS0 4
V-SYNC SEPERATER (NOISE SHAPE)
61 FRP 18 HP1 19 HP2 20 HP3 21 HP4 22 HP5 23 HP6 74 PCGW
V-TIMING PULSE GENERATOR
71 SLSH1 72 SLSH2 81 SLSH3 99 CP1 100 CP2 36 HCK1A H-TIMING PULSE GENERATOR 37 HCK2A 38 HCK1B 39 HCK2B 34 HSTA 41 HSTB 42 CLR 43 ENB 44 VCK 45 PCG 62 XCLP1 63 XCLP2 64 PRG 66 SH1 67 SH2 68 SH3 69 SH4 76 NTPL 77 XWD 80 XHD
VSS1 10 VSS2 13 VSS3 15 VSS4 29 VSS5 40 VSS6 54 VSS7 65 VSS8 79 VSS10 87 VSS11 90 VSS12 93 VDD0 3
VDD1 28 VDD2 35 VDD3 53 VDD4 70 VDD5 78
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CXD2412AQ
Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Symbol N.C. N.C. VDD0 VSS0 TC1 FPD1 PEO1 PWM1 RPD1 VSS1 CKO1 CKI1 VSS2 TST6 VSS3 HSYNC VSYNC HP1 HP2 HP3 HP4 HP5 HP6 TST1 TST2 TST3 TST4 VDD1 VSS4 TST5 XCLR RGT XRGT HSTA VDD2 HCK1A HCK2A I/O -- -- -- -- I O O I O -- O I -- I -- I I I I I I I I I I I I -- -- I I I O O -- O O Not connected Not connected Power supply GND FPD1 pin pulse width adjustment Phase comparator output B-1 (for NTSC/PAL) Loop filter integrator output 1 Loop filter integrator input 1 Phase comparator output A-1 (for NTSC/PAL) GND NTSC/PAL oscillation cell output NTSC/PAL oscillation cell input GND Test GND Hsync input (negative polarity) Vsync input (negative polarity) Switches for the horizontal display start position Switches for the horizontal display start position Switches for the horizontal display start position Switches for the horizontal display start position Switches for the horizontal display start position Switches for the horizontal display start position Test Test Test Test Power supply GND Test Cleared at 0 V Right/left inversion identification signal input Right/left inversion identification signal output H start pulse A Power supply H clock pulse 1A H clock pulse 2A -3- H H H L L L L L H L L L L L Description Input pin for open status
CXD2412AQ
Pin No. 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74
Symbol HCK1B HCK2B VSS5 HSTB CLR ENB VCK PCG VST DWN N.C. VP1 VP2 N.C. N.C. VDD3 VSS6 N.C. N.C. N.C. N.C. N.C. N.C. FRP XCLP1 XCLP2 PRG VSS7 SH1 SH2 SH3 SH4 VDD4 SLSH1 SLSH2 SLAUX PCGW
I/O O O -- O O O O O O I -- I I -- -- -- -- -- -- -- -- -- -- O O O O -- O O O O -- I I I I H clock pulse 1B H clock pulse 2B GND H start pulse B Clear pulse Enable pulse V clock pulse Precharge pulse V start pulse
Description
Input pin for open status
Up/down inversion identification signal input Not connected Switches for the vertical display start position Switches for the vertical display start position Not connected Not connected Power supply GND Not connected Not connected Not connected Not connected Not connected Not connected AC drive inversion timing output Video signal pedestal clamp pulse 1 Video signal pedestal clamp pulse 2 Precharge signal pulse GND Sample-and-hold pulse 1 Sample-and-hold pulse 2 Sample-and-hold pulse 3 Resample-and-hold pulse Power supply Switches SH Switches SH Switches free-running identification line number Switches PCG -4-
H
L H
L L H H
CXD2412AQ
Pin No. 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
Symbol SLFR NTPL XWD VDD5 VSS8 XHD SLSH3 TC2 FPD2 PEO2 PWM2 RPD2 VSS10 CKO2 CKI2 VSS11 CKO3 CKI3 VSS12 RPD3 PEO3 PWM3 FPD3 TC3 CP1 CP2
I/O I I I -- -- I I I O O I O -- O I -- O I -- O O I O I I I
Description Switches between H inversion and F inversion (H: H inversion / L: F inversion) Switches mode Switches mode Power supply GND Switches mode Switches SH FPD2 pin pulse width adjustment Phase comparator output B-2 (for WIDE) Loop filter integrator output 2 Loop filter integrator input 2 Phase comparator output A-2 (for WIDE) GND WIDE oscillation cell output WIDE oscillation cell input GND HD/MNDC oscillation cell output HD/MNDC oscillation cell input GND Phase comparator output A-3 (for HD/MNDC) Loop filter integrator output 3 Loop filter integrator input 3 Phase comparator output B-3 (for HD/MNDC) FPD3 pin pulse width adjustment Switches pedestal clamp position Switches pedestal clamp position
Input pin for open status H H H
H L
H L
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CXD2412AQ
Electrical Characteristics 1. DC characteristics Item Supply voltage Input voltage Input voltage Input voltage Input voltage Output voltage Output voltage Output voltage Output voltage Output voltage Output voltage Input leak current Input leak current Output leak current Symbol VDD VIH VIL VIH VIL VOH VOL VOH VOL VOH VOL IIL IIH ILZ TTL input cell TTL input cell CMOS input cell CMOS input cell IOH = -4mA (HCKl, SHm) IOL = 8mA (HCKl, SHm) IOH = -3mA (CKOn, CKIn) IOL = 3mA (CKOn, CKIn) IOH = -2mA (other than the above) IOL = 4mA (other than the above) Pull-up resistor connected Pull-down resistor connected RPDn, FPDn (at high impedance state) HD mode, VDD = 5.0V (at no load) -40 -40 -40 75 -100 100 VDD - 0.8 0.4 -240 240 40 VDD/2 VDD/2 VDD - 0.8 0.4 0.7VDD 0.3VDD Conditions (Temperature = 25C, Vss = 0V) Min. 4.5 2.2 0.8 Typ. Max. 5.5 Unit V V V V V V V V V V V A A A mA
Current consumption IDD
2. AC characteristics Item Clock input cycle Cross point time difference Cross point time difference Output rise delay Output fall delay Output rise delay Output fall delay Applicable pins CKIn HCK1A, HCK2A HCK1B, HCK2B HCKl, SHm HCKl, SHm t t tpr tpf CL = 30pF CL = 30pF CL = 30pF CL = 30pF CL = 30pF CL = 30pF CL = 30pF CL = 30pF CL = 30pF CL = 30pF CL = 30pF CL = 30pF 0.05 1 0.1 1 45 45 Symbol Conditions Min. 22
(VDD = 5.0 10%) Typ. Max. Unit ns 10 10 20 15 25 15 0.25 5 0.5 5 52 52 ns ns ns ns ns ns ns ns ns ns % %
Other than HCK1 and SHm tpr Other than HCK1 and SHm tpf dt1 dt2 dt1 dt2 tH/tH + tL tH/tH + tL
HCK1, SH1 delay time difference HCK1A, HCK1B, SH1 HCK1, SH1 delay time difference HCK1A, HCK1B, SH1 HCK2, SH1 delay time difference HCK2A, HCK2B, SH1 HCK2, SH1 delay time difference HCK2A, HCK2B, SH1 HCK1 Duty HCK2 Duty Note) l = 1A, 1B, 2A, 2B n = 1, 2, 3 m = 1, 2, 3, 4 HCK1A, HCK1B HCK2A, HCK1B
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CXD2412AQ
Timing Definition
CK1
VDD 0V VDD Output 0V tpr VDD Output 0V tpf
VDD HCK1A (HCK2A) 50% 50% 0V VDD HCK1B (HCK2B) 50% 50% 0V t t
t CK1
t
HCK1A 1B 2A 2B t1
50%
50%
50%
tH
t2
tL
SH1
50%
50%
dt1
dt2
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LCD Panel Structure
The structure of LCD panels driven by this IC is shown below. Dot Arrangement (1) (16 : 9 display) The dots are arranged in a delta pattern. The shaded area is used for the dark border around the display. The R corresponds to SIG2, G to SIG1, and B to SIG3, respectively.
ODD = 1094 EVEN = 1095 ODD = 1069 EVEN = 1068 ODD = 135 EVEN = 134
Side Black 2 44 45 46 47 48 311 312 313 314 4:3 Area Side Black 356 357 DR1 DR2 DR3 DR4
GATE SW GATE SW GATE SW GATE SW
ODD = 13 EVEN = 14 ODD = 799 EVEN = 800 ODD = 135 EVEN = 134
ODD = 13 EVEN = 13
DL1
DL2
DL3
DL4
1
GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW
GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW
GBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR R GB RGBRGB RGBRGB RGBRGB RGB RGB RGB RGBRGBRGB RGBRGB RGB
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R GB R GB R GB R GB R GB RGBRGB RGBRGB RGBRGB RGBRGB RGBRGB RGBRGB RGBRGB RGB RGB RGBRGB RGBRGB RGB RGB RGBRGB RGBRGB RGB RGB RGBRGB RGBRGB RGB RGB RGBRGB RGBRGB RGB RGB R GB R GB R GB RGBRGB RGBRGB RGBRGB RGBRGB RGBRGB RGB RGB RGBRGB RGBRGB RGB RGB RGBRGB RGBRGB RGB RGB
3
RGB RGBRGBRGBRGB RGB RGB
GBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR
1
2
RGB RGB RGBR GB RGB RGB RGB R GB RGB RGB RGB R GB RGB R GB RGB RGB RGB RGB RGB RGB RGB RGB RGB GBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR RGB RGB RGB RGB RGB RGBRGBRGB RGBRGB RGB RGBRGBRGB RGBRGB RGB RGBRGBRGB RGBRGB RGB RGBRGBRGB RGBRGB RGB RGBRGBRGB RGBRGB RGB
3
RGB RGBRGBRGBRGB RGB RGB
4
GBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR
RGB RGBRGBRGBRGB RGB RGB
GBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR
RGB RGBRGBRGBRGB RGB RGB
480
GBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR
RGB RGBRGBRGBRGB RGB RGB
GBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR
RGB RGBRGBRGBRGB RGB RGB
GBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR
RGB RGB RGBR GB RGB RGB RGB R GB RGB RGB RGB R GB RGB R GB RGB RGB RGB RGB RGB RGB RGB RGB RGB GBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR RGB RGB RGB RGBRGBRGB RGBRGB RGB RGBRGBRGB RGBRGB RGB RGBRGBRGB RGBRGB RGB
479 480
RGB RGBRGBRGBRGB RGB RGB
GBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR
RGB RGBRGBRGBRGB RGB RGB
3
GBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR
RGB RGBRGBRGBRGB RGB RGB
CXD2412AQ
Dot Arrangement (2) (4 : 3 display) The dots are arranged in a delta pattern. The shaded area is used for the dark border around the display. The R corresponds to SIG2, G to SIG1, and B to SIG3, respectively.
ODD = 1094 EVEN = 1095 ODD = 1069 EVEN = 1068 ODD = 135 EVEN = 134
Side Black 2 44 45 46 47 48 311 312 313 314 356 4:3 Area Side Black 357 DR1 DR2 DR3 DR4
GATE SW GATE SW GATE SW GATE SW
ODD = 13 EVEN = 14 ODD = 799 EVEN = 800 ODD = 135 EVEN = 134
ODD = 13 EVEN = 13
DL1
DL2
DL3
DL4
1
GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW
GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW GATE SW
GBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR R GB RGBRGB RGBRGB RGBRGB RGB RGB RGB RGBRGBRGB RGBRGB RGB
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R GB R GB R GB R GB R GB RGBRGB RGBRGB RGBRGB RGBRGB RGBRGB RGBRGB RGBRGB RGB RGB RGBRGB RGBRGB RGB RGB RGBRGB RGBRGB RGB RGB RGBRGB RGBRGB RGB RGB RGBRGB RGBRGB RGB RGB R GB R GB R GB RGBRGB RGBRGB RGBRGB RGBRGB RGBRGB RGB RGB RGBRGB RGBRGB RGB RGB RGBRGB RGBRGB RGB RGB
3
RGB RGBRGBRGBRGB RGB RGB
GBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR
1
2
RGB RGB RGBR GB RGB RGB RGB R GB RGB RGB RGB R GB RGB R GB RGB RGB RGB RGB RGB RGB RGB RGB RGB GBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR RGB RGB RGB RGB RGB RGBRGBRGB RGBRGB RGB RGBRGBRGB RGBRGB RGB RGBRGBRGB RGBRGB RGB RGBRGBRGB RGBRGB RGB RGBRGBRGB RGBRGB RGB
3
RGB RGBRGBRGBRGB RGB RGB
4
GBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR
RGB RGBRGBRGBRGB RGB RGB
GBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR
RGB RGBRGBRGBRGB RGB RGB
480
GBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR
RGB RGBRGBRGBRGB RGB RGB
GBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR
RGB RGBRGBRGBRGB RGB RGB
GBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR
RGB RGB RGBR GB RGB RGB RGB R GB RGB RGB RGB R GB RGB R GB RGB RGB RGB RGB RGB RGB RGB RGB RGB GBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR RGB RGB RGB RGBRGBRGB RGBRGB RGB RGBRGBRGB RGBRGB RGB RGBRGBRGB RGBRGB RGB
479 480
RGB RGBRGBRGBRGB RGB RGB
GBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR
RGB RGBRGBRGBRGB RGB RGB
3
GBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBRGBR
RGB RGBRGBRGBRGB RGB RGB
CXD2412AQ
CXD2412AQ
Input Signal Specifications 1. Horizontal sync signal * With NTSC, NTSC WIDE, PAL, PAL+, and MNDC, the standard signal is doubled in speed, and a 1/2 cycle, 1/2 width horizontal sync signal (H.SYNC) is input. * With HD, a signal derived by cutting off the lower part of 3-value sync is input. * Negative polarity input is used. 2. Vertical sync signal * V.sync separated by synchronizing separation circuit and not doubled in speed is input as the vertical sync signal. * Negative polarity input is used. * With this TG, the phase relationship between VSYNC and HSYNC is as follows;
(1) NTSC/NTSC WIDE/MNDC
Phase reference
HSYNC (Double-speed H.sync)
VSYNC
(2) PAL/PAL+
Phase reference
HSYNC (Double-speed H.sync )
VSYNC
The video signal has a 487-line effective period due to scanning line conversion.
(3) HD
ODD FIELD
HSYNC
VSYNC
EVEN FIELD
Phase reference
HSYNC
VSYNC
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CXD2412AQ
Mode Selection Mode selection is performed by means of three pins, as shown in the table. NTPL H L H L L H XWD H H L L X X XHD H H H H L L Mode NTSC PAL NTSC WIDE PAL+ HD MNDC
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CXD2412AQ
SH Pulse Switching The phase relationship between HCK1A, HCK1B and SH1, SH2, SH3, SH4 is switched by SLSH1, SLSH2, SLSH3.
SLSH1 = L SLSH2 = L SLSH3 = L Right scan driver RGT = H HCK1A (HCK1B) SLSH1 = H SLSH2 = L SLSH3 = L SLSH1 = L SLSH2 = H SLSH3 = L SLSH1 = H SLSH2 = H SLSH3 = L
SH1
SH2
SH3
SH4
Left scan driver RGT = L HCK1A (HCK1B)
SH1
SH2
SH3
SH4
- 12 -
CXD2412AQ
SLSH1 = L SLSH2 = L SLSH3 = H Right scan driver RGT = H HCK1A (HCK1B)
SLSH1 = H SLSH2 = L SLSH3 = H
SLSH1 = L SLSH2 = H SLSH3 = H
SLSH1 = H SLSH2 = H SLSH3 = H
SH1
SH2
SH3
SH4
Left scan driver RGT = L HCK1A (HCK1B)
SH1
SH2
SH3
SH4
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CXD2412AQ
Right/Left Inversion and Up/Down Inversion The LCD panel is arranged in a delta pattern, where an identical signal line is 1.5-dot offset for every horizontal line. For this reason, a 1.5-bit offset is made to the horizontal start pulse HST of the LCD between lines. HCK and S/H (sample and hold) are also 1.5-bit offset in a similar manner. When the panel is driven with right/left inversion or up/down inversion, this offset relationship becomes inverted for even and odd lines. Moreover, since the dot arrangement is asymmetrical, the HST position is also offset. Right/left inversion and up/down inversion are supported by the TG as follows. (1) Two types of output pulses for right scan (A output) and left scan (B output) are prepared for HST, HCK to allow right/left inversion present/absent mixed three-panel LCDs to be driven simultaneously. In addition, XRGT (RGT inverse output) is prepared for the left scan panel. SH1 and SH3 connections to the driver are reversed for sample-and-hold. (2) Left scan pulses are output to the A output by setting the right/left inversion input pin RGT to low. Also, XRGT is driven high by setting RGT to low. (3) The A and B outputs output up scan pulses by setting the up/down inversion input pin DWN to low.
Right scan Left scan Right/left inversion compatible SH wiring diagram SH1 H SCANNER SH1 SH2 Down scan TG SH2 SH3 SH4 A output driver
V SCANNER
SH3 SH4
Display area
SH1 SH2 SH3 SH4 B output driver
Up scan
The relationship between the output pins and switches is summarized below. TG input pin DWN H H L L RGT H L H L For right scan, down scan For left scan, down scan For right scan, up scan For left scan, up scan B output HST, HCK (Three-panel LCD auxiliary output) For left scan, down scan For right scan, down scan For left scan, up scan For right scan, up scan
A output HST, HCK
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CXD2412AQ
Horizontal Output Pulses The HST pulses are offset for each line in accordance with the dot arrangement.
Video start
MCK
-2fh HSTn n = A.B -3.5fh
16 : 9, right, down scan, odd line 16 : 9, left, down scan, odd line 16 : 9, right, up scan, even line 16 : 9, left, up scan, even line
16 : 9, right, down scan, even line 16 : 9, right, up scan, odd line -0.5fh 16 : 9, left, down scan, even line 16 : 9, left, up scan, odd line -5fh 4 : 3, right, down scan, odd line 4 : 3, left, down scan, odd line 4 : 3, right, up scan, even line 4 : 3, left, up scan, even line
-6.5fh 4 : 3, right, down scan, even line 4 : 3, right, up scan, odd line -3.5fh 4 : 3, left, down scan, even line 4 : 3, left, up scan, odd line
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CXD2412AQ
The phase relationship between the horizontal pulses is shown in the figure below. The display start position can be changed by means of the HP pin while maintaining this relationship.
HSYNC
HSTn n = A.B
VCK FRP 1s
PCG 1.2s 0.7s
FRP
PRG
ENB 0.4s
CLR 3.1s
XCLP1 0.55s 1.2s
XCLP2 0.15s 2s
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CXD2412AQ
XCLP Pulse Switching The phase relationship between HSYNC and XCLP1, XCLP2 is switched by means of CP1 and CP2.
-250ns
550ns
1350ns
2150ns
-650ns
150ns
950ns
1750ns
2550ns
HSYNC
XCLP1
CP1 = L; CP2 = L
Central value
CP1 = H; CP2 = L
CP1 = L; CP2 = H
CP1 = H; CP2 = H
XCLP2
CP1 = L; CP2 = L
Central value
CP1 = H; CP2 = L
CP1 = L; CP2 = H
CP1 = H; CP2 = H
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CXD2412AQ
Vertical Output The vertical display position is varied as shown below. VP1 L H L H VP2 L L H H After 2H After 1H Central value 1H before
LCD Panel AC Driving for No Signal With no signal, also, provision is made as follows for AC driving of the LCD panel. Horizontal pulses The PLL is set to the free-running state. Therefore, the horizontal pulse frequency depends on the PLL free-running frequency. Vertical pulses The number of lines is counted by an internal counter, and VST and FRP are output in a specific cycle.
VST Cycle with No Signal SLAUX = L NTSC NTSC-WIDE MNDC PAL PAL+ HD SLAUX = H All modes 769H 545H
641H 577H
Note) This TG determines there to be no signal if there is no VSYNC input during the above cycle.
- 18 -
NTSC-ODD LINE
925 935 965 0 20 30 50 60 80 90 110 120 140 150 170 945 955 10 40 70 100 130 160
Horizontal Direction Timing Chart
885
895
905
915
MCK
HSYNC
XCLP1
XCLP2
SH1
SH2
SH3
SH4
HCK1A
HCK2A
- 19 -
HSTA
HCK1B
HCK2B
HSTB
ENB
CLR
VCK
FRP
PCG
PRG
CXD2412AQ
Note) Input pins in default state.
NTSC-EVEN LINE
925 935 945 965 0 20 50 30 80 60 110 90 140 120 170 150 955 10 40 70 100 130 160
Horizontal Direction Timing Chart
885
895
905
915
MCK
HSYNC
XCLP1
XCLP2
SH1
SH2
SH3
SH4
HCK1A
HCK2A
- 20 -
HSTA
HCK1B
HCK2B
HSTB
ENB
CLR
VCK
FRP
PCG
PRG
CXD2412AQ
Note) Input pins in default state.
PAL-ODD LINE
969 979 40 50 190 989 10 20 80 100 130 110 160 140 170 0 30 60 70 90 120 150 180
Horizontal Direction Timing Chart
929
939
949
959
MCK
HSYNC
XCLP1
XCLP2
SH1
SH2
SH3
SH4
HCK1A
HCK2A
- 21 -
HSTA
HCK1B
HCK2B
HSTB
ENB
CLR
VCK
FRP
PCG
PRG
CXD2412AQ
Note) Input pins in default state.
PAL-EVEN LINE
969 979 989 10 20 30 40 50 100 110 130 160 140 190 170 80 0 60 70 90 120 150 180
Horizontal Direction Timing Chart
929
939
949
959
MCK
HSYNC
XCLP1
XCLP2
SH1
SH2
SH3
SH4
HCK1A
HCK2A
- 22 -
HSTA
HCK1B
HCK2B
HSTB
ENB
CLR
VCK
FRP
PCG
PRG
CXD2412AQ
Note) Input pins in default state.
NT-WIDE-ODD LINE
10 30 60 90 120 130 150 160 20 40 70 50 100 80 110 140
Horizontal Direction Timing Chart
1205 1215 1225 1235 1245 1255 1265 1275 1285 1295 0
MCK
HSYNC
XCLP1
XCLP2
SH1
SH2
SH3
SH4
HCK1A
HCK2A
- 23 -
HSTA
HCK1B
HCK2B
HSTB
ENB
CLR
VCK
FRP
PCG
PRG
CXD2412AQ
Note) Input pins in default state.
NT-WIDE-EVEN LINE
10 30 60 90 120 130 150 160 20 40 50 70 80 100 110 140
Horizontal Direction Timing Chart
1205 1215 1225 1235 1245 1255 1265 1275 1285 1295 0
MCK
HSYNC
XCLP1
XCLP2
SH1
SH2
SH3
SH4
HCK1A
HCK2A
- 24 -
HSTA
HCK1B
HCK2B
HSTB
ENB
CLR
VCK
FRP
PCG
PRG
CXD2412AQ
Note) Input pins in default state.
PAL+ -ODD LINE
10 30 60 90 120 130 150 160 20 40 50 70 80 100 110 140
Horizontal Direction Timing Chart
1235 1245 1255 1265 1275 1285 1295 1305 1315 1325 0
MCK
HSYNC
XCLP1
XCLP2
SH1
SH2
SH3
SH4
HCK1A
HCK2A
- 25 -
HSTA
HCK1B
HCK2B
HSTB
ENB
CLR
VCK
FRP
PCG
PRG
CXD2412AQ
Note) Input pins in default state.
PAL+ -EVEN LINE
10 30 60 90 120 130 150 160 20 40 50 70 80 100 110 140
Horizontal Direction Timing Chart
1235 1245 1255 1265 1275 1285 1295 1305 1315 1325 0
MCK
HSYNC
XCLP1
XCLP2
SH1
SH2
SH3
SH4
HCK1A
HCK2A
- 26 -
HSTA
HCK1B
HCK2B
HSTB
ENB
CLR
VCK
FRP
PCG
PRG
CXD2412AQ
Note) Input pins in default state.
HD-ODD LINE
10 30 60 80 90 110 120 140 150 180 210 20 40 50 70 100 130 160 170 190 200 220
Horizontal Direction Timing Chart
1280 1290 1300 1310 0
MCK
HSYNC
XCLP1
XCLP2
SH1
SH2
SH3
SH4
HCK1A
HCK2A
- 27 -
HSTA
HCK1B
HCK2B
HSTB
ENB
CLR
VCK
FRP
PCG
PRG
CXD2412AQ
Note) Input pins in default state.
HD-EVEN LINE
10 30 60 80 110 90 140 120 150 180 210 20 40 70 50 100 130 160 170 190 220 200
Horizontal Direction Timing Chart
1280 1290 1300 1310 0
MCK
HSYNC
XCLP1
XCLP2
SH1
SH2
SH3
SH4
HCK1A
HCK2A
- 28 -
HSTA
HCK1B
HCK2B
HSTB
ENB
CLR
VCK
FRP
PCG
PRG
CXD2412AQ
Note) Input pins in default state.
MNDC-ODD LINE
10 30 20 40 60 90 120 150 70 50 100 80 130 110 160 140
Horizontal Direction Timing Chart
1277 1287 1297 1307 1317 1327 1337 1347 1357 1367 0
MCK
HSYNC
XCLP1
XCLP2
SH1
SH2
SH3
SH4
HCK1A
HCK2A
- 29 -
HSTA
HCK1B
HCK2B
HSTB
ENB
CLR
VCK
FRP
PCG
PRG
CXD2412AQ
Note) Input pins in default state.
MNDC-EVEN LINE
10 30 20 40 60 90 120 150 70 50 100 80 130 110 160 140
Horizontal Direction Timing Chart
1277 1287 1297 1307 1317 1327 1337 1347 1357 1367 0
MCK
HSYNC
XCLP1
XCLP2
SH1
SH2
SH3
SH4
HCK1A
HCK2A
- 30 -
HSTA
HCK1B
HCK2B
HSTB
ENB
CLR
VCK
FRP
PCG
PRG
CXD2412AQ
Note) Input pins in default state.
NTSC/NTSC WIDE/MNDC
Vertical Direction Timing Chart
HSYNC (Double-speed sync) VSYNC Start of display 21H
1 2' 3 4' 5 6' 7 8'
BLK
482 483'
XCLP
VST
12345
1st display line
VCK
- 31 -
FRP (H inversion) FRP (F inversion)
HST
ENB
Vres (Internal pulse)
CXD2412AQ
PAL/PAL+
Vertical Direction Timing Chart
HSYNC Start of display 20H
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
VSYNC
BLK
XCLP
VST
1st display line
- 32 -
VCK
12345
FRP (H inversion) FRP (F inversion)
HST
ENB
Vres (Internal pulse)
CXD2412AQ
HD-ODD FIELD
Vertical Direction Timing Chart
HSYNC Start of display 45H
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
VSYNC
BLK
1035
XCLP
VST
1st display line
- 33 -
VCK
12345
FRP (H inversion)
FRP (F inversion)
HST
ENB
Vres (Internal pulse)
CXD2412AQ
HD-EVEN FIELD
Vertical Direction Timing Chart
HSYNC Start of display
VSYNC
BLK
518 523 528 533 538
517
XCLP
VST
1st display line
VCK
12345
- 34 -
FRP (H inversion)
FRP (F inversion)
HST
ENB
Vres (Internal pulse)
CXD2412AQ
+5.0V
H H XHD XWID NTPL SLFR PCGW RGT SLAUX SLSH2 SLSH1 VP2 VP1 DWN H H H H H H H H H H H SLSH3
Application Circuit
L
L
L L
L
L
L
L
L
L
L
L
L
47 16V 0.01 47 16V 0.01
47 16V 0.01
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
XHD VSS VDD XWID NTPL SLFR PCGW SLAUX SLSH2 SLSH1 VDD SH4 SH3 SH2 SH1 VSS PRG XCLP2 XCLP1 FRP N.C. N.C. N.C. N.C. N.C. N.C. VSS VDD N.C. N.C.
81 82 83 84 85 86 87 88 89 90 91 92 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 49
20p
0.5
SLSH3 TC2 FPD2 PEO2 PWM2 RPD2 VSS CKO2
VP2 VP1 N.C. DWN VST PCG VCK
50
0.1
33k
1000p
+13.0V
5.1k 0.01
93 94 95 96 97 98 99 100
N.C. N.C. VDD VSS TC1 FPD1 PEO1 PWM1 RPD1 VSS CKO1 CKI1 VSS TST6 VSS HSYNC VSYNC HP1 HP2 HP3 HP4 HP5 HP6 TST1 TST2 TST3 TST4 VDD VSS TST5
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
47 16V 0.01 CKI2 VSS CKO3 CKI3 VSS RPD3 PEO3 PWM3 FPD3 TC3 CP1 CP2
1 2 3 8 5 4 7 9 6
- 35 -
+5.0V 47 16V 0.01 5.1k 0.1 0.5 33k 33k +13.0V 0.01 50k 10k 20p 0.01 0.01 3.3 33k 1000p 10k 33 25V 1k 33k 33k 1000p 5.1k 0.1 1 1245 10k 10k 10k 10k +13.0V 0.01 50k 10k 33k 0.01 20p C HP3 S1030 TOP VIEW
1k
33 25V
33k
10k
50k
10k
3.3
0.01
0.01
33k
ENB CLR HSTB VSS HCK2B HCK1B HCK2A HCK1A VDD HSTA XRGT RGT XCLR
31
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
+5.0V
0.01
47 16V
+5.0V
0.01 +5.0V
33 25V
50k
50k
50k
100p
100p
100p
H
H
H
H
1k
10k
L HP2
L HP1
L CP1
L CP2
33 25V
CXD2412AQ
0.01
3.3
CXD2412AQ
Package Outline
Unit: mm
100PIN QFP (PLASTIC)
+ 0.1 0.15 - 0.05
23.9 0.4 + 0.4 20.0 - 0.1
+ 0.4 14.0 - 0.01 17.9 0.4
15.8 0.4
A
0.65 0.12 M
+ 0.35 2.75 - 0.15
0.15
0 to 15 DETAIL A
0.8 0.2
(16.3)
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-100P-L01 QFP100-P-1420-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING COPPER / 42 ALLOY 1.4g
- 36 -

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